The present invention relates to a front end signal processing method and apparatus for processing signals from a variety of image sensors such as a CCD (Charge Coupled Device) image sensor.
Conventionally, a front end signal processor having a circuit configuration as illustrated in FIG. 6 has been up used for processing signals from an image sensor such as a CCD image sensor. Specifically, as illustrated, the conventional front end signal processor comprises a correlated double sampler CDS coupled to receive an input (CCD Input) from a CCD image sensor; an analog programmable gain amplifier PGA; and an analog-to-digital (AID) converter ADC. As can be seen, the analog programmable gain amplifier PGA is located between the correlated double sampler CDS and the A/D converter ADC so as to amplify sampled signals in an analog form and input the amplified signals to the AID converter ADC. Some analog programmable gain amplifiers may include a logarithmic amplifier (or a logarithmic attenuator) which has a gain characteristic exhibiting a linear gain curve for a gain control signal, when represented in dB, for amplifying (or attenuating) signals from a correlated double sampler. The gain curve is typically plotted in logarithmic scale because of the characteristic of human's visual sense to the brightness. In this event, the programmable gain amplifier contains a special amplifier or attenuator for imposing the logarithmic characteristic on the gain characteristic with respect to a control signal (PGACONT). Also, the conventional front end signal processor comprises a feedback loop including an optical black (OB) clamp circuit OBCLAMP and a capacitor CAP for storing a black level in order to clamp the black level of a luminance signal from an image sensor. As illustrated, since the feedback loop is formed such that the input or output of the AID converter (the input is only shown in FIG. 6) is fed back to the correlated double sampler CDS or the programmable gain amplifier PGA (indicated by a solid line and a dotted line, respectively), a gain stage such as the programmable gain amplifier PGA is often contained in the feedback loop.
The conventional front end signal processor configured as described above encounters difficulties in improving the performance of the logarithmic amplifier (or logarithmic attenuator) arranged in the analog programmable gain amplifier and hence difficulties in providing a linear gain curve, represented in dB, which is required for the logarithmic amplifier. Also, the gain curve presented by the logarithmic amplifier highly depends on variations in devices introduced in course of the manufacturing, and may sometimes experience a larger deviation from a straight line. This is the main cause of reducing the yield of the entire front end signal processor. Further, the programmable gain amplifier block consumes significant power in order to ensure the linearity and sufficient noise performance for the logarithmic amplifier.
Furthermore, since the conventional signal processor described above contains the analog programmable gain amplifier which includes an amplifier such as a logarithmic amplifier within the optical black clamp feedback loop, a convergence time constant of the loop largely varies depending on the gain of the amplifier. A correction to the variations in the gain involves complicated analog processing such as insertion of an amplifier having a gain reverse to the gain of the amplifier within the programmable gain amplifier into the feedback loop to fix the time constant.
For the reason set forth above, conventional front end signal processors generally require high power consumption in a range of 150 to 200 mW, and very few require power consumption lower than 100 mW.